********** Mapped Logic ********** |
A(0) <= NOT (((NOT wra(0) AND xclk)
OR (NOT xclk AND NOT rda(0)))); |
A(1) <= NOT (((xclk AND NOT wra(1))
OR (NOT xclk AND NOT rda(1)))); |
A(2) <= NOT (((xclk AND NOT wra(2))
OR (NOT xclk AND NOT rda(2)))); |
A(3) <= NOT (((xclk AND NOT wra(3))
OR (NOT xclk AND NOT rda(3)))); |
A(4) <= NOT (((xclk AND NOT wra(4))
OR (NOT xclk AND NOT rda(4)))); |
A(5) <= NOT (((xclk AND NOT wra(5))
OR (NOT xclk AND NOT rda(5)))); |
A(6) <= NOT (((xclk AND NOT wra(6))
OR (NOT xclk AND NOT rda(6)))); |
A(7) <= NOT (((xclk AND NOT wra(7))
OR (NOT xclk AND NOT rda(7)))); |
A(8) <= NOT (((xclk AND NOT wra(8))
OR (NOT xclk AND NOT rda(8)))); |
A(9) <= NOT (((xclk AND NOT wra(9))
OR (NOT xclk AND NOT rda(9)))); |
A(10) <= NOT (((xclk AND NOT wra(10))
OR (NOT xclk AND NOT rda(10)))); |
A(11) <= NOT (((xclk AND NOT wra(11))
OR (NOT xclk AND NOT rda(11)))); |
A(12) <= NOT (((xclk AND NOT wra(12))
OR (NOT xclk AND NOT rda(12)))); |
A(13) <= NOT (((xclk AND NOT wra(13))
OR (NOT xclk AND NOT rda(13)))); |
A(14) <= NOT (((xclk AND NOT wra(14))
OR (NOT xclk AND NOT rda(14)))); |
A(15) <= NOT (((xclk AND NOT wra(15))
OR (NOT xclk AND NOT rda(15)))); |
A(16) <= NOT (((xclk AND NOT wra(16))
OR (NOT xclk AND NOT rda(16)))); |
A(17) <= NOT (((xclk AND NOT wra(17))
OR (NOT xclk AND NOT rda(17)))); |
A(18) <= NOT (((xclk AND NOT wra(18))
OR (NOT xclk AND NOT rda(18)))); |
FDCPE_D0: FDCPE port map (D_I(0),udat(0),xclk,'0','0',D_CE(0));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= xclk; D_CE(0) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D1: FDCPE port map (D_I(1),udat(1),xclk,'0','0',D_CE(1));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= xclk; D_CE(1) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D2: FDCPE port map (D_I(2),udat(2),xclk,'0','0',D_CE(2));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= xclk; D_CE(2) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D3: FDCPE port map (D_I(3),udat(3),xclk,'0','0',D_CE(3));
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= xclk; D_CE(3) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D4: FDCPE port map (D_I(4),udat(4),xclk,'0','0',D_CE(4));
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= xclk; D_CE(4) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D5: FDCPE port map (D_I(5),udat(5),xclk,'0','0',D_CE(5));
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= xclk; D_CE(5) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D6: FDCPE port map (D_I(6),udat(6),xclk,'0','0',D_CE(6));
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= xclk; D_CE(6) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D7: FDCPE port map (D_I(7),rxd,xclk,'0','0',D_CE(7));
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= xclk; D_CE(7) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); |
FDCPE_D8: FDCPE port map (D_I(8),udat(0),xclk,'0','0',D_CE(8));
D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= xclk; D_CE(8) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D9: FDCPE port map (D_I(9),udat(1),xclk,'0','0',D_CE(9));
D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= xclk; D_CE(9) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D10: FDCPE port map (D_I(10),udat(2),xclk,'0','0',D_CE(10));
D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= xclk; D_CE(10) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D11: FDCPE port map (D_I(11),udat(3),xclk,'0','0',D_CE(11));
D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= xclk; D_CE(11) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D12: FDCPE port map (D_I(12),udat(4),xclk,'0','0',D_CE(12));
D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= xclk; D_CE(12) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D13: FDCPE port map (D_I(13),udat(5),xclk,'0','0',D_CE(13));
D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= xclk; D_CE(13) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D14: FDCPE port map (D_I(14),udat(6),xclk,'0','0',D_CE(14));
D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= xclk; D_CE(14) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
FDCPE_D15: FDCPE port map (D_I(15),rxd,xclk,'0','0',D_CE(15));
D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= xclk; D_CE(15) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); |
LED <= NOT ((NOT wra(0) AND NOT wra(10) AND NOT wra(1) AND NOT wra(2) AND NOT wra(3) AND
NOT wra(4) AND NOT wra(5) AND NOT wra(6) AND NOT wra(7) AND NOT wra(8) AND NOT wra(9) AND NOT wra(11) AND wra(12) AND wra(13) AND NOT wra(14) AND wra(15) AND NOT wra(16) AND NOT wra(17) AND wra(18))); |
N_PZ_639 <= ((rcnt(3) AND rcnt(9))
OR (rcnt(9) AND rcnt(4)) OR (rcnt(9) AND rcnt(1)) OR (rcnt(9) AND rcnt(5)) OR (rcnt(9) AND rcnt(2)) OR (rcnt(9) AND rcnt(6)) OR (rcnt(9) AND rcnt(7)) OR (rcnt(9) AND rcnt(8)) OR (pcnt(8) AND pcnt(9)) OR (NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(9) AND NOT pcnt(7)) OR (NOT pcnt(8) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7)) OR (NOT rcnt(9) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (pcnt(2) AND pcnt(5) AND pcnt(6) AND pcnt(9) AND pcnt(7)) OR (pcnt(3) AND pcnt(5) AND pcnt(6) AND pcnt(9) AND pcnt(7)) OR (pcnt(5) AND pcnt(4) AND pcnt(6) AND pcnt(9) AND pcnt(7)) OR (NOT pcnt(2) AND NOT pcnt(3) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(9) AND NOT pcnt(7)) OR (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT rcnt(1) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8))); |
N_PZ_653 <= ((NOT pcnt(8))
OR (NOT pcnt(9)) OR (NOT pcnt(5) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(7)) OR (NOT pcnt(2) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(6) AND NOT pcnt(7)) OR (NOT pcnt(1) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(6) AND NOT pcnt(7))); |
N_PZ_677 <= ((ucnt(1) AND NOT ucnt(3) AND udiv(0) AND udiv(1) AND
udiv(2)) OR (ucnt(2) AND NOT ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND NOT ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); |
N_PZ_935 <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND
NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
N_PZ_936 <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND
NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
RD <= NOT ((NOT xclk AND yclk)); |
WR <= NOT ((rxcf AND xclk AND NOT yclk)); |
LDCP_blu0: LDCP port map (blu(0),D(11).PIN,NOT xclk,'0','0'); |
LDCP_blu1: LDCP port map (blu(1),D(12).PIN,NOT xclk,'0','0'); |
LDCP_blu2: LDCP port map (blu(2),D(13).PIN,NOT xclk,'0','0'); |
LDCP_blu3: LDCP port map (blu(3),D(14).PIN,NOT xclk,'0','0'); |
LDCP_blu4: LDCP port map (blu(4),D(15).PIN,NOT xclk,'0','0'); |
LDCP_grn0: LDCP port map (grn(0),D(5).PIN,NOT xclk,'0','0'); |
LDCP_grn1: LDCP port map (grn(1),D(6).PIN,NOT xclk,'0','0'); |
LDCP_grn2: LDCP port map (grn(2),D(7).PIN,NOT xclk,'0','0'); |
LDCP_grn3: LDCP port map (grn(3),D(8).PIN,NOT xclk,'0','0'); |
LDCP_grn4: LDCP port map (grn(4),D(9).PIN,NOT xclk,'0','0'); |
LDCP_grn5: LDCP port map (grn(5),D(10).PIN,NOT xclk,'0','0'); |
hsync <= ((NOT pcnt(8))
OR (NOT pcnt(9)) OR (NOT pcnt(2) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(7)) OR (NOT pcnt(1) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(7))); |
pclk <= (xclk AND yclk); |
FDCPE_pcnt0: FDCPE port map (pcnt(0),pcnt_D(0),xclk,'0','0','1');
pcnt_D(0) <= (N_PZ_653 AND NOT pcnt(0)); |
FDCPE_pcnt1: FDCPE port map (pcnt(1),pcnt_D(1),xclk,'0','0','1');
pcnt_D(1) <= ((N_PZ_653 AND pcnt(1) AND NOT pcnt(0)) OR (N_PZ_653 AND NOT pcnt(1) AND pcnt(0))); |
FTCPE_pcnt2: FTCPE port map (pcnt(2),pcnt_T(2),xclk,'0','0','1');
pcnt_T(2) <= ((NOT N_PZ_653 AND pcnt(2)) OR (N_PZ_653 AND pcnt(1) AND pcnt(0))); |
FDCPE_pcnt3: FDCPE port map (pcnt(3),pcnt_D(3),xclk,'0','0','1');
pcnt_D(3) <= (N_PZ_653 AND pcnt(3)) XOR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0)); |
FDCPE_pcnt4: FDCPE port map (pcnt(4),pcnt_D(4),xclk,'0','0','1');
pcnt_D(4) <= (N_PZ_653 AND pcnt(4)) XOR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3)); |
FTCPE_pcnt5: FTCPE port map (pcnt(5),pcnt_T(5),xclk,'0','0','1');
pcnt_T(5) <= ((pcnt(5) AND pcnt(8) AND pcnt(9)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND NOT pcnt(8) AND pcnt(4)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(4) AND NOT pcnt(9))); |
FTCPE_pcnt6: FTCPE port map (pcnt(6),pcnt_T(6),xclk,'0','0','1');
pcnt_T(6) <= ((pcnt(8) AND pcnt(6) AND pcnt(9)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND NOT pcnt(8) AND pcnt(4)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(4) AND NOT pcnt(9))); |
FTCPE_pcnt7: FTCPE port map (pcnt(7),pcnt_T(7),xclk,'0','0','1');
pcnt_T(7) <= ((NOT N_PZ_653 AND pcnt(7)) OR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(4) AND pcnt(6))); |
FTCPE_pcnt8: FTCPE port map (pcnt(8),pcnt_T(8),xclk,'0','0','1');
pcnt_T(8) <= ((NOT N_PZ_653) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(4) AND pcnt(6) AND pcnt(7))); |
FDCPE_pcnt9: FDCPE port map (pcnt(9),pcnt_D(9),xclk,'0','0','1');
pcnt_D(9) <= ((N_PZ_653 AND pcnt(9)) OR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(8) AND pcnt(4) AND pcnt(6) AND pcnt(7))); |
FDCPE_rcnt0: FDCPE port map (rcnt(0),rcnt_D(0),xclk,'0','0','1');
rcnt_D(0) <= ((N_PZ_653 AND rcnt(0)) OR (NOT rcnt(9) AND NOT N_PZ_653 AND NOT rcnt(0)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); |
FTCPE_rcnt1: FTCPE port map (rcnt(1),rcnt_T(1),xclk,'0','0','1');
rcnt_T(1) <= (rcnt(9) AND NOT N_PZ_653 AND rcnt(1)) XOR ((NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(0)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(6) AND rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); |
FTCPE_rcnt2: FTCPE port map (rcnt(2),rcnt_T(2),xclk,'0','0','1');
rcnt_T(2) <= (rcnt(9) AND NOT N_PZ_653 AND rcnt(2)) XOR ((NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(0)) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(1) AND NOT rcnt(5) AND rcnt(2) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(5) AND rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); |
FTCPE_rcnt3: FTCPE port map (rcnt(3),rcnt_T(3),xclk,'0','0','1');
rcnt_T(3) <= ((rcnt(3) AND rcnt(9) AND NOT N_PZ_653) OR (NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(2) AND rcnt(0)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND NOT rcnt(5) AND rcnt(2) AND NOT rcnt(6) AND rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); |
FTCPE_rcnt4: FTCPE port map (rcnt(4),rcnt_T(4),xclk,'0','0','1');
rcnt_T(4) <= ((rcnt(9) AND rcnt(4) AND NOT N_PZ_653) OR (rcnt(3) AND NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(2) AND rcnt(0))); |
FTCPE_rcnt5: FTCPE port map (rcnt(5),rcnt_T(5),xclk,'0','0','1');
rcnt_T(5) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(5)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(2) AND rcnt(0))); |
FTCPE_rcnt6: FTCPE port map (rcnt(6),rcnt_T(6),xclk,'0','0','1');
rcnt_T(6) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(6)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(0))); |
FTCPE_rcnt7: FTCPE port map (rcnt(7),rcnt_T(7),xclk,'0','0','1');
rcnt_T(7) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(7)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(6) AND rcnt(0))); |
FTCPE_rcnt8: FTCPE port map (rcnt(8),rcnt_T(8),xclk,'0','0','1');
rcnt_T(8) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(8)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(6) AND rcnt(0) AND rcnt(7))); |
FDCPE_rcnt9: FDCPE port map (rcnt(9),rcnt_D(9),xclk,'0','0','1');
rcnt_D(9) <= ((rcnt(9) AND N_PZ_653) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(6) AND rcnt(0) AND rcnt(7) AND rcnt(8))); |
FTCPE_rda0: FTCPE port map (rda(0),NOT N_PZ_639,xclk,rda_CLR(0),'0','1');
rda_CLR(0) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda1: FTCPE port map (rda(1),rda_T(1),xclk,rda_CLR(1),'0','1');
rda_T(1) <= (rda(0) AND NOT N_PZ_639); rda_CLR(1) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda2: FTCPE port map (rda(2),rda_T(2),xclk,rda_CLR(2),'0','1');
rda_T(2) <= (rda(0) AND NOT N_PZ_639 AND rda(1)); rda_CLR(2) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda3: FTCPE port map (rda(3),rda_T(3),xclk,rda_CLR(3),'0','1');
rda_T(3) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2)); rda_CLR(3) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda4: FTCPE port map (rda(4),rda_T(4),xclk,rda_CLR(4),'0','1');
rda_T(4) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3)); rda_CLR(4) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda5: FTCPE port map (rda(5),rda_T(5),xclk,rda_CLR(5),'0','1');
rda_T(5) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4)); rda_CLR(5) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda6: FTCPE port map (rda(6),rda_T(6),xclk,rda_CLR(6),'0','1');
rda_T(6) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5)); rda_CLR(6) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda7: FTCPE port map (rda(7),rda_T(7),xclk,rda_CLR(7),'0','1');
rda_T(7) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6)); rda_CLR(7) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda8: FTCPE port map (rda(8),rda_T(8),xclk,rda_CLR(8),'0','1');
rda_T(8) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7)); rda_CLR(8) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda9: FTCPE port map (rda(9),rda_T(9),xclk,rda_CLR(9),'0','1');
rda_T(9) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8)); rda_CLR(9) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda10: FTCPE port map (rda(10),rda_T(10),xclk,rda_CLR(10),'0','1');
rda_T(10) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9)); rda_CLR(10) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda11: FTCPE port map (rda(11),rda_T(11),xclk,rda_CLR(11),'0','1');
rda_T(11) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9)); rda_CLR(11) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda12: FTCPE port map (rda(12),rda_T(12),xclk,rda_CLR(12),'0','1');
rda_T(12) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11)); rda_CLR(12) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda13: FTCPE port map (rda(13),rda_T(13),xclk,rda_CLR(13),'0','1');
rda_T(13) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12)); rda_CLR(13) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda14: FTCPE port map (rda(14),rda_T(14),xclk,rda_CLR(14),'0','1');
rda_T(14) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13)); rda_CLR(14) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda15: FTCPE port map (rda(15),rda_T(15),xclk,rda_CLR(15),'0','1');
rda_T(15) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14)); rda_CLR(15) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda16: FTCPE port map (rda(16),rda_T(16),xclk,rda_CLR(16),'0','1');
rda_T(16) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14) AND rda(15)); rda_CLR(16) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_rda17: FTCPE port map (rda(17),rda_T(17),xclk,N_PZ_936,'0','1');
rda_T(17) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14) AND rda(15) AND rda(16)); |
FTCPE_rda18: FTCPE port map (rda(18),rda_T(18),xclk,N_PZ_935,'0','1');
rda_T(18) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14) AND rda(15) AND rda(16) AND rda(17)); |
LDCP_red0: LDCP port map (red(0),D(0).PIN,NOT xclk,'0','0'); |
LDCP_red1: LDCP port map (red(1),D(1).PIN,NOT xclk,'0','0'); |
LDCP_red2: LDCP port map (red(2),D(2).PIN,NOT xclk,'0','0'); |
LDCP_red3: LDCP port map (red(3),D(3).PIN,NOT xclk,'0','0'); |
LDCP_red4: LDCP port map (red(4),D(4).PIN,NOT xclk,'0','0'); |
FDCPE_rxcf: FDCPE port map (rxcf,rxcf_D,xclk,'0','0','1');
rxcf_D <= ((rxcf AND udiv(0) AND udiv(1) AND udiv(2)) OR (rxcf AND NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0)) OR (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi)); |
FTCPE_rxhi: FTCPE port map (rxhi,rxhi_T,xclk,'0','0','1');
rxhi_T <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2)); |
FTCPE_ucnt0: FTCPE port map (ucnt(0),ucnt_T(0),xclk,'0','0','1');
ucnt_T(0) <= ((NOT ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0)) OR (NOT ucnt(1) AND NOT ucnt(2) AND udiv(0) AND udiv(1) AND udiv(2))); |
FTCPE_ucnt1: FTCPE port map (ucnt(1),ucnt_T(1),xclk,'0','0','1');
ucnt_T(1) <= ((ucnt(1) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT ucnt(2) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); |
FTCPE_ucnt2: FTCPE port map (ucnt(2),ucnt_T(2),xclk,'0','0','1');
ucnt_T(2) <= ((ucnt(2) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(1) AND NOT ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); |
FTCPE_ucnt3: FTCPE port map (ucnt(3),ucnt_T(3),xclk,'0','0','1');
ucnt_T(3) <= ((ucnt(1) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(2) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(1) AND ucnt(2) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); |
FDCPE_udat0: FDCPE port map (udat(0),udat(1),xclk,'0','0',N_PZ_677); |
FDCPE_udat1: FDCPE port map (udat(1),udat(2),xclk,'0','0',N_PZ_677); |
FDCPE_udat2: FDCPE port map (udat(2),udat(3),xclk,'0','0',N_PZ_677); |
FDCPE_udat3: FDCPE port map (udat(3),udat(4),xclk,'0','0',N_PZ_677); |
FDCPE_udat4: FDCPE port map (udat(4),udat(5),xclk,'0','0',N_PZ_677); |
FDCPE_udat5: FDCPE port map (udat(5),udat(6),xclk,'0','0',N_PZ_677); |
FDCPE_udat6: FDCPE port map (udat(6),rxd,xclk,'0','0',N_PZ_677); |
FTCPE_udiv0: FTCPE port map (udiv(0),udiv_T(0),xclk,'0','0','1');
udiv_T(0) <= NOT (((NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(0)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(1)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(2)))); |
FTCPE_udiv1: FTCPE port map (udiv(1),udiv_T(1),xclk,'0','0','1');
udiv_T(1) <= udiv(0) XOR ((NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND NOT udiv(1)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND NOT udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(0) AND udiv(1))); |
FTCPE_udiv2: FTCPE port map (udiv(2),udiv_T(2),xclk,'0','0','1');
udiv_T(2) <= (udiv(0) AND udiv(1)) XOR ((NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(0) AND NOT udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(1) AND NOT udiv(2)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND udiv(1) AND NOT udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); |
vsync <= NOT (((NOT rcnt(9) AND NOT rcnt(4) AND NOT rcnt(5) AND NOT rcnt(6) AND
NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)))); |
FTCPE_wra0: FTCPE port map (wra(0),'0',rxcf,wra_CLR(0),'0','1');
wra_CLR(0) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra1: FTCPE port map (wra(1),wra(0),rxcf,wra_CLR(1),'0','1');
wra_CLR(1) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra2: FTCPE port map (wra(2),wra_T(2),rxcf,wra_CLR(2),'0','1');
wra_T(2) <= (wra(0) AND wra(1)); wra_CLR(2) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra3: FTCPE port map (wra(3),wra_T(3),rxcf,wra_CLR(3),'0','1');
wra_T(3) <= (wra(0) AND wra(1) AND wra(2)); wra_CLR(3) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra4: FTCPE port map (wra(4),wra_T(4),rxcf,wra_CLR(4),'0','1');
wra_T(4) <= (wra(0) AND wra(1) AND wra(2) AND wra(3)); wra_CLR(4) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra5: FTCPE port map (wra(5),wra_T(5),rxcf,wra_CLR(5),'0','1');
wra_T(5) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4)); wra_CLR(5) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra6: FTCPE port map (wra(6),wra_T(6),rxcf,wra_CLR(6),'0','1');
wra_T(6) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5)); wra_CLR(6) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra7: FTCPE port map (wra(7),wra_T(7),rxcf,wra_CLR(7),'0','1');
wra_T(7) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6)); wra_CLR(7) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra8: FTCPE port map (wra(8),wra_T(8),rxcf,wra_CLR(8),'0','1');
wra_T(8) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7)); wra_CLR(8) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra9: FTCPE port map (wra(9),wra_T(9),rxcf,wra_CLR(9),'0','1');
wra_T(9) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8)); wra_CLR(9) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra10: FTCPE port map (wra(10),wra_T(10),rxcf,wra_CLR(10),'0','1');
wra_T(10) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9)); wra_CLR(10) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra11: FTCPE port map (wra(11),wra_T(11),rxcf,wra_CLR(11),'0','1');
wra_T(11) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9)); wra_CLR(11) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra12: FTCPE port map (wra(12),wra_T(12),rxcf,wra_CLR(12),'0','1');
wra_T(12) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11)); wra_CLR(12) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra13: FTCPE port map (wra(13),wra_T(13),rxcf,wra_CLR(13),'0','1');
wra_T(13) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12)); wra_CLR(13) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra14: FTCPE port map (wra(14),wra_T(14),rxcf,wra_CLR(14),'0','1');
wra_T(14) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13)); wra_CLR(14) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra15: FTCPE port map (wra(15),wra_T(15),rxcf,wra_CLR(15),'0','1');
wra_T(15) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14)); wra_CLR(15) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra16: FTCPE port map (wra(16),wra_T(16),rxcf,wra_CLR(16),'0','1');
wra_T(16) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14) AND wra(15)); wra_CLR(16) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra17: FTCPE port map (wra(17),wra_T(17),rxcf,wra_CLR(17),'0','1');
wra_T(17) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14) AND wra(15) AND wra(16)); wra_CLR(17) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wra18: FTCPE port map (wra(18),wra_T(18),rxcf,wra_CLR(18),'0','1');
wra_T(18) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14) AND wra(15) AND wra(16) AND wra(17)); wra_CLR(18) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); |
FTCPE_wrst0: FTCPE port map (wrst(0),wrst_T(0),xclk,rxcf,'0','1');
wrst_T(0) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_wrst1: FTCPE port map (wrst(1),wrst_T(1),xclk,rxcf,'0','1');
wrst_T(1) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); |
FTCPE_wrst2: FTCPE port map (wrst(2),wrst_T(2),xclk,rxcf,'0','1');
wrst_T(2) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8) AND wrst(1)); |
FTCPE_wrst3: FTCPE port map (wrst(3),wrst_T(3),xclk,rxcf,'0','1');
wrst_T(3) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8) AND wrst(1) AND wrst(2)); |
FTCPE_wrst4: FTCPE port map (wrst(4),wrst_T(4),xclk,rxcf,'0','1');
wrst_T(4) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8) AND wrst(1) AND wrst(2) AND wrst(3)); |
FDDCPE_xclk: FDDCPE port map (xclk,yclk,iclk,'0','0','1'); |
FDDCPE_yclk: FDDCPE port map (yclk,NOT xclk,iclk,'0','0','1'); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |