cpldfit: version J.40 Xilinx Inc. Fitter Report Design Name: main Date: 6- 3-2012, 6:52PM Device Used: XC2C256-7-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 143/256 ( 56%) 281 /896 ( 31%) 312 /640 ( 49%) 113/256 ( 44%) 59 /118 ( 50%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/16* 18/40 42/56 6/ 6* 1/1* 0/1 0/1 1/1* FB2 16/16* 38/40* 18/56 0/ 8 1/1* 1/1* 0/1 0/1 FB3 16/16* 38/40* 30/56 6/ 6* 1/1* 1/1* 0/1 0/1 FB4 16/16* 28/40 49/56 0/ 8 1/1* 1/1* 0/1 0/1 FB5 16/16* 24/40 18/56 0/ 5 1/1* 1/1* 0/1 0/1 FB6 16/16* 35/40 39/56 0/ 8 1/1* 1/1* 0/1 0/1 FB7 1/16 8/40 3/56 0/ 8 1/1* 1/1* 0/1 0/1 FB8 8/16 9/40 9/56 8/ 8* 1/1* 0/1 0/1 0/1 FB9 8/16 22/40 18/56 8/ 8* 1/1* 0/1 0/1 1/1* FB10 9/16 22/40 19/56 9/ 9* 1/1* 0/1 0/1 1/1* FB11 8/16 19/40 16/56 8/ 8* 1/1* 0/1 0/1 1/1* FB12 0/16 0/40 0/56 0/ 6 0/1 0/1 0/1 0/1 FB13 0/16 0/40 0/56 0/ 8 0/1 0/1 0/1 0/1 FB14 4/16 22/40 9/56 4/ 8 1/1* 0/1 0/1 0/1 FB15 2/16 21/40 3/56 1/ 7 1/1* 0/1 0/1 0/1 FB16 7/16 8/40 8/56 7/ 7* 1/1* 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 143/256 312/640 281/896 57/118 14/16 6/16 0/16 4/16 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 1/3 0/1 0/4 Signal 'iclk' mapped onto global clock net GCK2. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 1 1 | I/O : 57 108 Output : 41 41 | GCK/IO : 1 3 Bidirectional : 16 16 | GTS/IO : 0 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | CDR/IO : 0 1 GSR : 0 0 | DGE/IO : 0 1 ---- ---- Total 59 59 End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 57 Outputs ** Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State D<14> 4 10 FB1_3 143 GSR/I/O I/O LVCMOS33 KPR FAST DEFF RESET D<15> 4 10 FB1_4 142 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<5> 4 10 FB1_6 140 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<4> 4 10 FB1_12 139 I/O I/O LVCMOS33 KPR FAST DEFF RESET A<9> 2 3 FB1_13 138 I/O O LVCMOS33 FAST A<10> 2 3 FB1_14 137 I/O O LVCMOS33 FAST A<11> 2 3 FB3_1 136 I/O O LVCMOS33 FAST A<12> 2 3 FB3_2 135 I/O O LVCMOS33 FAST A<18> 2 3 FB3_3 134 I/O O LVCMOS33 FAST A<13> 2 3 FB3_5 133 I/O O LVCMOS33 FAST A<14> 2 3 FB3_14 132 I/O O LVCMOS33 FAST A<15> 2 3 FB3_16 131 I/O O LVCMOS33 FAST blu<4> 2 2 FB8_1 44 I/O O LVCMOS33 FAST LATCH RESET blu<3> 2 2 FB8_2 45 I/O O LVCMOS33 FAST LATCH RESET blu<2> 2 2 FB8_3 46 I/O O LVCMOS33 FAST LATCH RESET blu<1> 2 2 FB8_5 48 I/O O LVCMOS33 FAST LATCH RESET blu<0> 2 2 FB8_6 49 I/O O LVCMOS33 FAST LATCH RESET grn<5> 2 2 FB8_11 50 I/O O LVCMOS33 FAST LATCH RESET grn<4> 2 2 FB8_12 51 I/O O LVCMOS33 FAST LATCH RESET grn<3> 2 2 FB8_13 52 I/O O LVCMOS33 FAST LATCH RESET A<4> 2 3 FB9_1 112 I/O O LVCMOS33 FAST A<3> 2 3 FB9_2 113 I/O O LVCMOS33 FAST A<2> 2 3 FB9_4 114 I/O O LVCMOS33 FAST A<1> 2 3 FB9_6 115 I/O O LVCMOS33 FAST A<0> 2 3 FB9_12 116 I/O O LVCMOS33 FAST D<0> 4 10 FB9_13 117 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<1> 4 10 FB9_14 118 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<11> 4 10 FB9_15 119 I/O I/O LVCMOS33 KPR FAST DEFF RESET A<5> 2 3 FB10_1 111 I/O O LVCMOS33 FAST A<6> 2 3 FB10_2 110 I/O O LVCMOS33 FAST A<7> 2 3 FB10_3 107 I/O O LVCMOS33 FAST A<8> 2 3 FB10_4 106 I/O O LVCMOS33 FAST RD 1 2 FB10_5 105 I/O O LVCMOS33 FAST D<7> 4 10 FB10_6 104 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<6> 4 10 FB10_12 103 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<13> 4 10 FB10_14 102 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<12> 4 10 FB10_16 101 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<10> 4 10 FB11_5 120 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<8> 4 10 FB11_6 121 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<9> 4 10 FB11_11 124 I/O I/O LVCMOS33 KPR FAST DEFF RESET Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State D<2> 4 10 FB11_12 125 I/O I/O LVCMOS33 KPR FAST DEFF RESET D<3> 4 10 FB11_13 126 I/O I/O LVCMOS33 KPR FAST DEFF RESET WR 1 3 FB11_14 128 I/O O LVCMOS33 FAST A<17> 2 3 FB11_15 129 I/O O LVCMOS33 FAST A<16> 2 3 FB11_16 130 I/O O LVCMOS33 FAST pclk 1 2 FB14_6 68 I/O O LVCMOS33 FAST hsync 4 9 FB14_13 66 I/O O LVCMOS33 FAST vsync 2 10 FB14_14 64 I/O O LVCMOS33 FAST red<0> 2 2 FB14_16 61 I/O O LVCMOS33 FAST LATCH RESET LED 1 19 FB15_16 92 I/O O LVCMOS33 FAST red<1> 2 2 FB16_5 60 I/O O LVCMOS33 FAST LATCH RESET red<2> 2 2 FB16_6 59 I/O O LVCMOS33 FAST LATCH RESET red<3> 2 2 FB16_11 58 I/O O LVCMOS33 FAST LATCH RESET red<4> 2 2 FB16_12 57 I/O O LVCMOS33 FAST LATCH RESET grn<0> 2 2 FB16_13 56 I/O O LVCMOS33 FAST LATCH RESET grn<1> 2 2 FB16_15 54 I/O O LVCMOS33 FAST LATCH RESET grn<2> 2 2 FB16_16 53 I/O O LVCMOS33 FAST LATCH RESET ** 86 Buried Nodes ** Signal Total Total Loc Reg Reg Init Name Pts Inps Use State N_PZ_677 3 7 FB1_1 rxhi 2 8 FB1_2 TFF RESET ucnt<2> 3 8 FB1_5 TFF RESET ucnt<3> 4 8 FB1_7 TFF RESET ucnt<1> 4 8 FB1_8 TFF RESET udiv<0> 4 9 FB1_9 TFF RESET ucnt<0> 5 9 FB1_10 TFF RESET udiv<1> 5 9 FB1_11 TFF RESET udiv<2> 6 9 FB1_15 TFF RESET rxcf 4 11 FB1_16 DFF RESET rda<1> 3 23 FB2_1 TFF RESET rda<9> 3 31 FB2_2 TFF RESET rda<2> 3 24 FB2_3 TFF RESET rda<3> 3 25 FB2_4 TFF RESET rda<4> 3 26 FB2_5 TFF RESET rda<10> 3 32 FB2_6 TFF RESET rda<11> 3 33 FB2_7 TFF RESET rda<12> 3 34 FB2_8 TFF RESET rda<13> 3 35 FB2_9 TFF RESET rda<14> 3 36 FB2_10 TFF RESET rda<15> 3 37 FB2_11 TFF RESET rda<5> 3 27 FB2_12 TFF RESET rda<6> 3 28 FB2_13 TFF RESET rda<7> 3 29 FB2_14 TFF RESET rda<8> 3 30 FB2_15 TFF RESET rda<16> 3 38 FB2_16 TFF RESET udat<0> 3 3 FB3_4 DEFF RESET pcnt<4> 3 7 FB3_6 DFF RESET pcnt<3> 3 6 FB3_7 DFF RESET pcnt<2> 3 5 FB3_8 TFF RESET pcnt<1> 3 4 FB3_9 DFF RESET pcnt<0> 2 3 FB3_10 DFF RESET xclk 1 1 FB3_11 DDFF RESET yclk 1 1 FB3_12 DDFF RESET rda<18> 3 21 FB3_13 TFF RESET rda<17> 3 20 FB3_15 TFF RESET rcnt<7> 3 11 FB4_1 TFF RESET rcnt<1> 5 11 FB4_2 TFF RESET rcnt<8> 3 12 FB4_3 TFF RESET pcnt<9> 3 12 FB4_4 DFF RESET Signal Total Total Loc Reg Reg Init Name Pts Inps Use State rcnt<9> 4 12 FB4_5 DFF RESET rcnt<3> 4 12 FB4_6 TFF RESET N_PZ_936 1 20 FB4_7 N_PZ_935 1 20 FB4_8 rda<0> 3 22 FB4_9 TFF RESET wrst<0> 3 22 FB4_10 TFF RESET wrst<1> 3 23 FB4_11 TFF RESET rcnt<2> 6 12 FB4_12 TFF RESET wrst<2> 3 24 FB4_13 TFF RESET N_PZ_639 17 17 FB4_14 wrst<3> 3 25 FB4_15 TFF RESET wrst<4> 3 26 FB4_16 TFF RESET wra<8> 3 14 FB5_1 TFF RESET wra<3> 3 9 FB5_2 TFF RESET wra<9> 3 15 FB5_3 TFF RESET wra<4> 3 10 FB5_4 TFF RESET wra<5> 3 11 FB5_5 TFF RESET wra<6> 3 12 FB5_6 TFF RESET wra<10> 3 16 FB5_7 TFF RESET wra<11> 3 17 FB5_8 TFF RESET wra<12> 3 18 FB5_9 TFF RESET wra<13> 3 19 FB5_10 TFF RESET wra<14> 3 20 FB5_11 TFF RESET wra<15> 3 21 FB5_12 TFF RESET wra<16> 3 22 FB5_13 TFF RESET wra<7> 3 13 FB5_14 TFF RESET wra<17> 3 23 FB5_15 TFF RESET wra<18> 3 24 FB5_16 TFF RESET wra<1> 3 7 FB6_1 TFF RESET wra<0> 2 6 FB6_2 TFF RESET rcnt<6> 3 10 FB6_3 TFF RESET pcnt<5> 4 9 FB6_4 TFF RESET rcnt<5> 3 9 FB6_5 TFF RESET rcnt<4> 3 8 FB6_6 TFF RESET udat<5> 3 3 FB6_7 DEFF RESET udat<4> 3 3 FB6_8 DEFF RESET udat<3> 3 3 FB6_9 DEFF RESET udat<2> 3 3 FB6_10 DEFF RESET udat<1> 3 3 FB6_11 DEFF RESET N_PZ_653 5 9 FB6_12 Signal Total Total Loc Reg Reg Init Name Pts Inps Use State pcnt<6> 4 10 FB6_13 TFF RESET pcnt<8> 3 10 FB6_14 TFF RESET pcnt<7> 3 10 FB6_15 TFF RESET rcnt<0> 4 10 FB6_16 DFF RESET wra<2> 3 8 FB7_10 TFF RESET udat<6> 2 2 FB15_13 DEFF RESET ** 2 Inputs ** Signal Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style iclk FB6_4 38 GCK/I/O GCK LVCMOS33 KPR rxd FB15_13 87 I/O I LVCMOS33 KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 18/22 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 42/14 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use N_PZ_677 3 FB1_1 (b) (b) rxhi 2 FB1_2 (b) (b) + D<14> 4 FB1_3 143 GSR/I/O I/O + + D<15> 4 FB1_4 142 I/O I/O + + ucnt<2> 3 FB1_5 (b) (b) + D<5> 4 FB1_6 140 I/O I/O + + ucnt<3> 4 FB1_7 (b) (b) + ucnt<1> 4 FB1_8 (b) (b) + udiv<0> 4 FB1_9 (b) (b) + ucnt<0> 5 FB1_10 (b) (b) + udiv<1> 5 FB1_11 (b) (b) + D<4> 4 FB1_12 139 I/O I/O + + A<9> 2 FB1_13 138 I/O O A<10> 2 FB1_14 137 I/O O udiv<2> 6 FB1_15 (b) (b) + rxcf 4 FB1_16 (b) (b) + Signals Used by Logic in Function Block 1: rda<10> 7: ucnt<1> 13: udiv<0> 2: rda<9> 8: ucnt<2> 14: udiv<1> 3: rxcf 9: ucnt<3> 15: udiv<2> 4: rxd 10: udat<4> 16: wra<10> 5: rxhi 11: udat<5> 17: wra<9> 6: ucnt<0> 12: udat<6> 18: xclk Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs N_PZ_677 .....XXXX...XXX......................... 7 rxhi .....XXXX...XXX..X...................... 8 D<14> ....XXXXX..XXXX..X...................... 10 D<15> ...XXXXXX...XXX..X...................... 10 ucnt<2> .....XXXX...XXX..X...................... 8 D<5> ....XXXXX.X.XXX..X...................... 10 ucnt<3> .....XXXX...XXX..X...................... 8 ucnt<1> .....XXXX...XXX..X...................... 8 udiv<0> ...X.XXXX...XXX..X...................... 9 ucnt<0> ...X.XXXX...XXX..X...................... 9 udiv<1> ...X.XXXX...XXX..X...................... 9 D<4> ....XXXXXX..XXX..X...................... 10 A<9> .X..............XX...................... 3 A<10> X..............X.X...................... 3 udiv<2> ...X.XXXX...XXX..X...................... 9 rxcf ..XXXXXXX...XXX..X...................... 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 38/2 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 18/38 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use rda<1> 3 FB2_1 2 GTS/I/O (b) + + rda<9> 3 FB2_2 (b) (b) + + rda<2> 3 FB2_3 3 GTS/I/O (b) + + rda<3> 3 FB2_4 4 I/O (b) + + rda<4> 3 FB2_5 5 GTS/I/O (b) + + rda<10> 3 FB2_6 (b) (b) + + rda<11> 3 FB2_7 (b) (b) + + rda<12> 3 FB2_8 (b) (b) + + rda<13> 3 FB2_9 (b) (b) + + rda<14> 3 FB2_10 (b) (b) + + rda<15> 3 FB2_11 (b) (b) + + rda<5> 3 FB2_12 6 GTS/I/O (b) + + rda<6> 3 FB2_13 7 I/O (b) + + rda<7> 3 FB2_14 9 I/O (b) + + rda<8> 3 FB2_15 10 I/O (b) + + rda<16> 3 FB2_16 (b) (b) + + Signals Used by Logic in Function Block 1: N_PZ_639 14: rcnt<2> 27: rda<14> 2: pcnt<0> 15: rcnt<3> 28: rda<15> 3: pcnt<1> 16: rcnt<4> 29: rda<1> 4: pcnt<2> 17: rcnt<5> 30: rda<2> 5: pcnt<3> 18: rcnt<6> 31: rda<3> 6: pcnt<4> 19: rcnt<7> 32: rda<4> 7: pcnt<5> 20: rcnt<8> 33: rda<5> 8: pcnt<6> 21: rcnt<9> 34: rda<6> 9: pcnt<7> 22: rda<0> 35: rda<7> 10: pcnt<8> 23: rda<10> 36: rda<8> 11: pcnt<9> 24: rda<11> 37: rda<9> 12: rcnt<0> 25: rda<12> 38: xclk 13: rcnt<1> 26: rda<13> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs rda<1> XXXXXXXXXXXXXXXXXXXXXX...............X.. 23 rda<9> XXXXXXXXXXXXXXXXXXXXXX......XXXXXXXX.X.. 31 rda<2> XXXXXXXXXXXXXXXXXXXXXX......X........X.. 24 rda<3> XXXXXXXXXXXXXXXXXXXXXX......XX.......X.. 25 rda<4> XXXXXXXXXXXXXXXXXXXXXX......XXX......X.. 26 rda<10> XXXXXXXXXXXXXXXXXXXXXX......XXXXXXXXXX.. 32 rda<11> XXXXXXXXXXXXXXXXXXXXXXX.....XXXXXXXXXX.. 33 rda<12> XXXXXXXXXXXXXXXXXXXXXXXX....XXXXXXXXXX.. 34 rda<13> XXXXXXXXXXXXXXXXXXXXXXXXX...XXXXXXXXXX.. 35 rda<14> XXXXXXXXXXXXXXXXXXXXXXXXXX..XXXXXXXXXX.. 36 rda<15> XXXXXXXXXXXXXXXXXXXXXXXXXXX.XXXXXXXXXX.. 37 rda<5> XXXXXXXXXXXXXXXXXXXXXX......XXXX.....X.. 27 rda<6> XXXXXXXXXXXXXXXXXXXXXX......XXXXX....X.. 28 rda<7> XXXXXXXXXXXXXXXXXXXXXX......XXXXXX...X.. 29 rda<8> XXXXXXXXXXXXXXXXXXXXXX......XXXXXXX..X.. 30 rda<16> XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.. 38 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 38/2 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 30/26 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use A<11> 2 FB3_1 136 I/O O A<12> 2 FB3_2 135 I/O O A<18> 2 FB3_3 134 I/O O udat<0> 3 FB3_4 (b) (b) + A<13> 2 FB3_5 133 I/O O pcnt<4> 3 FB3_6 (b) (b) + pcnt<3> 3 FB3_7 (b) (b) + pcnt<2> 3 FB3_8 (b) (b) + pcnt<1> 3 FB3_9 (b) (b) + pcnt<0> 2 FB3_10 (b) (b) + xclk 1 FB3_11 (b) (b) yclk 1 FB3_12 (b) (b) rda<18> 3 FB3_13 (b) (b) + A<14> 2 FB3_14 132 I/O O rda<17> 3 FB3_15 (b) (b) + + A<15> 2 FB3_16 131 I/O O Signals Used by Logic in Function Block 1: N_PZ_639 14: rda<12> 27: rda<7> 2: N_PZ_653 15: rda<13> 28: rda<8> 3: N_PZ_677 16: rda<14> 29: rda<9> 4: N_PZ_935 17: rda<15> 30: udat<1> 5: N_PZ_936 18: rda<16> 31: wra<11> 6: pcnt<0> 19: rda<17> 32: wra<12> 7: pcnt<1> 20: rda<18> 33: wra<13> 8: pcnt<2> 21: rda<1> 34: wra<14> 9: pcnt<3> 22: rda<2> 35: wra<15> 10: pcnt<4> 23: rda<3> 36: wra<18> 11: rda<0> 24: rda<4> 37: xclk 12: rda<10> 25: rda<5> 38: yclk 13: rda<11> 26: rda<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs A<11> ............X.................X.....X... 3 A<12> .............X.................X....X... 3 A<18> ...................X...............XX... 3 udat<0> ..X..........................X......X... 3 A<13> ..............X.................X...X... 3 pcnt<4> .X...XXXXX..........................X... 7 pcnt<3> .X...XXXX...........................X... 6 pcnt<2> .X...XXX............................X... 5 pcnt<1> .X...XX.............................X... 4 pcnt<0> .X...X..............................X... 3 xclk .....................................X.. 1 yclk ....................................X... 1 rda<18> X..X......XXXXXXXXX.XXXXXXXXX.......X... 21 A<14> ...............X.................X..X... 3 rda<17> X...X.....XXXXXXXX..XXXXXXXXX.......X... 20 A<15> ................X.................X.X... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 28/12 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 49/7 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use rcnt<7> 3 FB4_1 11 I/O (b) + rcnt<1> 5 FB4_2 12 I/O (b) + rcnt<8> 3 FB4_3 13 I/O (b) + pcnt<9> 3 FB4_4 14 I/O (b) + rcnt<9> 4 FB4_5 15 I/O (b) + rcnt<3> 4 FB4_6 16 I/O (b) + N_PZ_936 1 FB4_7 (b) (b) N_PZ_935 1 FB4_8 (b) (b) rda<0> 3 FB4_9 (b) (b) + wrst<0> 3 FB4_10 (b) (b) + + wrst<1> 3 FB4_11 (b) (b) + + rcnt<2> 6 FB4_12 17 I/O (b) + wrst<2> 3 FB4_13 (b) (b) + + N_PZ_639 17 FB4_14 18 I/O (b) wrst<3> 3 FB4_15 (b) (b) + + wrst<4> 3 FB4_16 (b) (b) + + Signals Used by Logic in Function Block 1: N_PZ_639 11: pcnt<8> 20: rcnt<7> 2: N_PZ_653 12: pcnt<9> 21: rcnt<8> 3: pcnt<0> 13: rcnt<0> 22: rcnt<9> 4: pcnt<1> 14: rcnt<1> 23: rxcf 5: pcnt<2> 15: rcnt<2> 24: wrst<0> 6: pcnt<3> 16: rcnt<3> 25: wrst<1> 7: pcnt<4> 17: rcnt<4> 26: wrst<2> 8: pcnt<5> 18: rcnt<5> 27: wrst<3> 9: pcnt<6> 19: rcnt<6> 28: xclk 10: pcnt<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs rcnt<7> .X..........XXXXXXXX.X.....X............ 11 rcnt<1> .X..........XX.XXXXXXX.....X............ 11 rcnt<8> .X..........XXXXXXXXXX.....X............ 12 pcnt<9> .XXXXXXXXXXX...............X............ 12 rcnt<9> .X..........XXXXXXXXXX.....X............ 12 rcnt<3> .X..........XXXXXXXXXX.....X............ 12 N_PZ_936 ..XXXXXXXXXXXXXXXXXXXX.................. 20 N_PZ_935 ..XXXXXXXXXXXXXXXXXXXX.................. 20 rda<0> X.XXXXXXXXXXXXXXXXXXXX.....X............ 22 wrst<0> ..XXXXXXXXXXXXXXXXXXXXX....X............ 22 wrst<1> ..XXXXXXXXXXXXXXXXXXXXXX...X............ 23 rcnt<2> .X..........XXXXXXXXXX.....X............ 12 wrst<2> ..XXXXXXXXXXXXXXXXXXXXXXX..X............ 24 N_PZ_639 ....XXXXXXXX.XXXXXXXXX.................. 17 wrst<3> ..XXXXXXXXXXXXXXXXXXXXXXXX.X............ 25 wrst<4> ..XXXXXXXXXXXXXXXXXXXXXXXXXX............ 26 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 24/16 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 18/38 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use wra<8> 3 FB5_1 (b) (b) + + wra<3> 3 FB5_2 33 I/O (b) + + wra<9> 3 FB5_3 (b) (b) + + wra<4> 3 FB5_4 32 GCK/I/O (b) + + wra<5> 3 FB5_5 31 I/O (b) + + wra<6> 3 FB5_6 30 GCK/I/O (b) + + wra<10> 3 FB5_7 (b) (b) + + wra<11> 3 FB5_8 (b) (b) + + wra<12> 3 FB5_9 (b) (b) + + wra<13> 3 FB5_10 (b) (b) + + wra<14> 3 FB5_11 (b) (b) + + wra<15> 3 FB5_12 (b) (b) + + wra<16> 3 FB5_13 (b) (b) + + wra<7> 3 FB5_14 28 I/O (b) + + wra<17> 3 FB5_15 (b) (b) + + wra<18> 3 FB5_16 (b) (b) + + Signals Used by Logic in Function Block 1: rxcf 9: wra<16> 17: wra<7> 2: wra<0> 10: wra<17> 18: wra<8> 3: wra<10> 11: wra<1> 19: wra<9> 4: wra<11> 12: wra<2> 20: wrst<0> 5: wra<12> 13: wra<3> 21: wrst<1> 6: wra<13> 14: wra<4> 22: wrst<2> 7: wra<14> 15: wra<5> 23: wrst<3> 8: wra<15> 16: wra<6> 24: wrst<4> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs wra<8> XX........XXXXXXX..XXXXX................ 14 wra<3> XX........XX.......XXXXX................ 9 wra<9> XX........XXXXXXXX.XXXXX................ 15 wra<4> XX........XXX......XXXXX................ 10 wra<5> XX........XXXX.....XXXXX................ 11 wra<6> XX........XXXXX....XXXXX................ 12 wra<10> XX........XXXXXXXXXXXXXX................ 16 wra<11> XXX.......XXXXXXXXXXXXXX................ 17 wra<12> XXXX......XXXXXXXXXXXXXX................ 18 wra<13> XXXXX.....XXXXXXXXXXXXXX................ 19 wra<14> XXXXXX....XXXXXXXXXXXXXX................ 20 wra<15> XXXXXXX...XXXXXXXXXXXXXX................ 21 wra<16> XXXXXXXX..XXXXXXXXXXXXXX................ 22 wra<7> XX........XXXXXX...XXXXX................ 13 wra<17> XXXXXXXXX.XXXXXXXXXXXXXX................ 23 wra<18> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 35/5 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 39/17 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use wra<1> 3 FB6_1 34 I/O (b) + wra<0> 2 FB6_2 35 CDR/I/O (b) + rcnt<6> 3 FB6_3 (b) (b) + pcnt<5> 4 FB6_4 38 GCK/I/O GCK + rcnt<5> 3 FB6_5 (b) (b) + rcnt<4> 3 FB6_6 (b) (b) + udat<5> 3 FB6_7 (b) (b) + udat<4> 3 FB6_8 (b) (b) + udat<3> 3 FB6_9 (b) (b) + udat<2> 3 FB6_10 (b) (b) + udat<1> 3 FB6_11 (b) (b) + N_PZ_653 5 FB6_12 39 DGE/I/O (b) pcnt<6> 4 FB6_13 40 I/O (b) + pcnt<8> 3 FB6_14 41 I/O (b) + pcnt<7> 3 FB6_15 42 I/O (b) + rcnt<0> 4 FB6_16 43 I/O (b) + Signals Used by Logic in Function Block 1: N_PZ_653 13: rcnt<0> 25: udat<3> 2: N_PZ_677 14: rcnt<1> 26: udat<4> 3: pcnt<0> 15: rcnt<2> 27: udat<5> 4: pcnt<1> 16: rcnt<3> 28: udat<6> 5: pcnt<2> 17: rcnt<4> 29: wra<0> 6: pcnt<3> 18: rcnt<5> 30: wrst<0> 7: pcnt<4> 19: rcnt<6> 31: wrst<1> 8: pcnt<5> 20: rcnt<7> 32: wrst<2> 9: pcnt<6> 21: rcnt<8> 33: wrst<3> 10: pcnt<7> 22: rcnt<9> 34: wrst<4> 11: pcnt<8> 23: rxcf 35: xclk 12: pcnt<9> 24: udat<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs wra<1> ......................X.....XXXXXX...... 7 wra<0> ......................X......XXXXX...... 6 rcnt<6> X...........XXXXXXX..X............X..... 10 pcnt<5> ..XXXXXX..XX......................X..... 9 rcnt<5> X...........XXXXXX...X............X..... 9 rcnt<4> X...........XXXXX....X............X..... 8 udat<5> .X.........................X......X..... 3 udat<4> .X........................X.......X..... 3 udat<3> .X.......................X........X..... 3 udat<2> .X......................X.........X..... 3 udat<1> .X.....................X..........X..... 3 N_PZ_653 ...XXXXXXXXX............................ 9 pcnt<6> ..XXXXXXX.XX......................X..... 10 pcnt<8> X.XXXXXXXX........................X..... 10 pcnt<7> X.XXXXXXXX........................X..... 10 rcnt<0> X...........X..XXXXXXX............X..... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 8/32 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 3/53 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 (b) (unused) 0 FB7_2 (b) (unused) 0 FB7_3 (b) (unused) 0 FB7_4 (b) (unused) 0 FB7_5 26 I/O (unused) 0 FB7_6 25 I/O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) wra<2> 3 FB7_10 (b) (b) + + (unused) 0 FB7_11 24 I/O (unused) 0 FB7_12 23 I/O (unused) 0 FB7_13 22 I/O (unused) 0 FB7_14 21 I/O (unused) 0 FB7_15 20 I/O (unused) 0 FB7_16 19 I/O Signals Used by Logic in Function Block 1: rxcf 4: wrst<0> 7: wrst<3> 2: wra<0> 5: wrst<1> 8: wrst<4> 3: wra<1> 6: wrst<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs wra<2> XXXXXXXX................................ 8 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 9/31 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 9/47 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use blu<4> 2 FB8_1 44 I/O O + blu<3> 2 FB8_2 45 I/O O + blu<2> 2 FB8_3 46 I/O O + (unused) 0 FB8_4 (b) blu<1> 2 FB8_5 48 I/O O + blu<0> 2 FB8_6 49 I/O O + (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) grn<5> 2 FB8_11 50 I/O O + grn<4> 2 FB8_12 51 I/O O + grn<3> 2 FB8_13 52 I/O O + (unused) 0 FB8_14 (b) (unused) 0 FB8_15 (b) (unused) 0 FB8_16 (b) Signals Used by Logic in Function Block 1: D<10>.PIN 4: D<13>.PIN 7: D<8>.PIN 2: D<11>.PIN 5: D<14>.PIN 8: D<9>.PIN 3: D<12>.PIN 6: D<15>.PIN 9: xclk Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs blu<4> .....X..X............................... 2 blu<3> ....X...X............................... 2 blu<2> ...X....X............................... 2 blu<1> ..X.....X............................... 2 blu<0> .X......X............................... 2 grn<5> X.......X............................... 2 grn<4> .......XX............................... 2 grn<3> ......X.X............................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB9 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 22/18 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 18/38 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use A<4> 2 FB9_1 112 I/O O A<3> 2 FB9_2 113 I/O O (unused) 0 FB9_3 (b) A<2> 2 FB9_4 114 I/O O (unused) 0 FB9_5 (b) A<1> 2 FB9_6 115 I/O O (unused) 0 FB9_7 (b) (unused) 0 FB9_8 (b) (unused) 0 FB9_9 (b) (unused) 0 FB9_10 (b) (unused) 0 FB9_11 (b) A<0> 2 FB9_12 116 I/O O D<0> 4 FB9_13 117 I/O I/O + + D<1> 4 FB9_14 118 I/O I/O + + D<11> 4 FB9_15 119 I/O I/O + + (unused) 0 FB9_16 (b) Signals Used by Logic in Function Block 1: rda<0> 9: ucnt<2> 16: udiv<2> 2: rda<1> 10: ucnt<3> 17: wra<0> 3: rda<2> 11: udat<0> 18: wra<1> 4: rda<3> 12: udat<1> 19: wra<2> 5: rda<4> 13: udat<3> 20: wra<3> 6: rxhi 14: udiv<0> 21: wra<4> 7: ucnt<0> 15: udiv<1> 22: xclk 8: ucnt<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs A<4> ....X...............XX.................. 3 A<3> ...X...............X.X.................. 3 A<2> ..X...............X..X.................. 3 A<1> .X...............X...X.................. 3 A<0> X...............X....X.................. 3 D<0> .....XXXXXX..XXX.....X.................. 10 D<1> .....XXXXX.X.XXX.....X.................. 10 D<11> .....XXXXX..XXXX.....X.................. 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB10 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 22/18 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 19/37 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use A<5> 2 FB10_1 111 I/O O A<6> 2 FB10_2 110 I/O O A<7> 2 FB10_3 107 I/O O A<8> 2 FB10_4 106 I/O O RD 1 FB10_5 105 I/O O D<7> 4 FB10_6 104 I/O I/O + + (unused) 0 FB10_7 (b) (unused) 0 FB10_8 (b) (unused) 0 FB10_9 (b) (unused) 0 FB10_10 (b) (unused) 0 FB10_11 (b) D<6> 4 FB10_12 103 I/O I/O + + (unused) 0 FB10_13 (b) D<13> 4 FB10_14 102 I/O I/O + + (unused) 0 FB10_15 (b) D<12> 4 FB10_16 101 I/O I/O + + Signals Used by Logic in Function Block 1: rda<5> 9: ucnt<2> 16: udiv<2> 2: rda<6> 10: ucnt<3> 17: wra<5> 3: rda<7> 11: udat<4> 18: wra<6> 4: rda<8> 12: udat<5> 19: wra<7> 5: rxd 13: udat<6> 20: wra<8> 6: rxhi 14: udiv<0> 21: xclk 7: ucnt<0> 15: udiv<1> 22: yclk 8: ucnt<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs A<5> X...............X...X................... 3 A<6> .X...............X..X................... 3 A<7> ..X...............X.X................... 3 A<8> ...X...............XX................... 3 RD ....................XX.................. 2 D<7> ....XXXXXX...XXX....X................... 10 D<6> .....XXXXX..XXXX....X................... 10 D<13> .....XXXXX.X.XXX....X................... 10 D<12> .....XXXXXX..XXX....X................... 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB11 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 19/21 Number of function block control terms used/remaining: 2/2 Number of PLA product terms used/remaining: 16/40 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB11_1 (b) (unused) 0 FB11_2 (b) (unused) 0 FB11_3 (b) (unused) 0 FB11_4 (b) D<10> 4 FB11_5 120 I/O I/O + + D<8> 4 FB11_6 121 I/O I/O + + (unused) 0 FB11_7 (b) (unused) 0 FB11_8 (b) (unused) 0 FB11_9 (b) (unused) 0 FB11_10 (b) D<9> 4 FB11_11 124 I/O I/O + + D<2> 4 FB11_12 125 I/O I/O + + D<3> 4 FB11_13 126 I/O I/O + + WR 1 FB11_14 128 I/O O A<17> 2 FB11_15 129 I/O O A<16> 2 FB11_16 130 I/O O Signals Used by Logic in Function Block 1: rda<16> 8: ucnt<3> 14: udiv<1> 2: rda<17> 9: udat<0> 15: udiv<2> 3: rxcf 10: udat<1> 16: wra<16> 4: rxhi 11: udat<2> 17: wra<17> 5: ucnt<0> 12: udat<3> 18: xclk 6: ucnt<1> 13: udiv<0> 19: yclk 7: ucnt<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs D<10> ...XXXXX..X.XXX..X...................... 10 D<8> ...XXXXXX...XXX..X...................... 10 D<9> ...XXXXX.X..XXX..X...................... 10 D<2> ...XXXXX..X.XXX..X...................... 10 D<3> ...XXXXX...XXXX..X...................... 10 WR ..X..............XX..................... 3 A<17> .X..............XX...................... 3 A<16> X..............X.X...................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB12 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB12_1 (b) (unused) 0 FB12_2 100 I/O (unused) 0 FB12_3 (b) (unused) 0 FB12_4 (b) (unused) 0 FB12_5 (b) (unused) 0 FB12_6 (b) (unused) 0 FB12_7 (b) (unused) 0 FB12_8 (b) (unused) 0 FB12_9 (b) (unused) 0 FB12_10 (b) (unused) 0 FB12_11 98 I/O (unused) 0 FB12_12 97 I/O (unused) 0 FB12_13 96 I/O (unused) 0 FB12_14 95 I/O (unused) 0 FB12_15 94 I/O (unused) 0 FB12_16 (b) *********************************** FB13 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB13_1 75 I/O (unused) 0 FB13_2 76 I/O (unused) 0 FB13_3 77 I/O (unused) 0 FB13_4 (b) (unused) 0 FB13_5 78 I/O (unused) 0 FB13_6 79 I/O (unused) 0 FB13_7 (b) (unused) 0 FB13_8 (b) (unused) 0 FB13_9 (b) (unused) 0 FB13_10 (b) (unused) 0 FB13_11 (b) (unused) 0 FB13_12 80 I/O (unused) 0 FB13_13 81 I/O (unused) 0 FB13_14 82 I/O (unused) 0 FB13_15 (b) (unused) 0 FB13_16 (b) *********************************** FB14 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 22/18 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 9/47 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB14_1 74 I/O (unused) 0 FB14_2 71 I/O (unused) 0 FB14_3 70 I/O (unused) 0 FB14_4 69 I/O (unused) 0 FB14_5 (b) pclk 1 FB14_6 68 I/O O (unused) 0 FB14_7 (b) (unused) 0 FB14_8 (b) (unused) 0 FB14_9 (b) (unused) 0 FB14_10 (b) (unused) 0 FB14_11 (b) (unused) 0 FB14_12 (b) hsync 4 FB14_13 66 I/O O vsync 2 FB14_14 64 I/O O (unused) 0 FB14_15 (b) red<0> 2 FB14_16 61 I/O O + Signals Used by Logic in Function Block 1: D<0>.PIN 9: pcnt<8> 16: rcnt<5> 2: pcnt<1> 10: pcnt<9> 17: rcnt<6> 3: pcnt<2> 11: rcnt<0> 18: rcnt<7> 4: pcnt<3> 12: rcnt<1> 19: rcnt<8> 5: pcnt<4> 13: rcnt<2> 20: rcnt<9> 6: pcnt<5> 14: rcnt<3> 21: xclk 7: pcnt<6> 15: rcnt<4> 22: yclk 8: pcnt<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs pclk ....................XX.................. 2 hsync .XXXXXXXXX.............................. 9 vsync ..........XXXXXXXXXX.................... 10 red<0> X...................X................... 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB15 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 21/19 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 3/53 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB15_1 (b) (unused) 0 FB15_2 83 I/O (unused) 0 FB15_3 (b) (unused) 0 FB15_4 (b) (unused) 0 FB15_5 (b) (unused) 0 FB15_6 (b) (unused) 0 FB15_7 (b) (unused) 0 FB15_8 (b) (unused) 0 FB15_9 (b) (unused) 0 FB15_10 (b) (unused) 0 FB15_11 85 I/O (unused) 0 FB15_12 86 I/O udat<6> 2 FB15_13 87 I/O I + (unused) 0 FB15_14 88 I/O (unused) 0 FB15_15 91 I/O LED 1 FB15_16 92 I/O O Signals Used by Logic in Function Block 1: N_PZ_677 8: wra<15> 15: wra<4> 2: wra<0> 9: wra<16> 16: wra<5> 3: wra<10> 10: wra<17> 17: wra<6> 4: wra<11> 11: wra<18> 18: wra<7> 5: wra<12> 12: wra<1> 19: wra<8> 6: wra<13> 13: wra<2> 20: wra<9> 7: wra<14> 14: wra<3> 21: xclk Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs LED .XXXXXXXXXXXXXXXXXXX.................... 19 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB16 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 8/32 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 8/48 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB16_1 (b) (unused) 0 FB16_2 (b) (unused) 0 FB16_3 (b) (unused) 0 FB16_4 (b) red<1> 2 FB16_5 60 I/O O + red<2> 2 FB16_6 59 I/O O + (unused) 0 FB16_7 (b) (unused) 0 FB16_8 (b) (unused) 0 FB16_9 (b) (unused) 0 FB16_10 (b) red<3> 2 FB16_11 58 I/O O + red<4> 2 FB16_12 57 I/O O + grn<0> 2 FB16_13 56 I/O O + (unused) 0 FB16_14 (b) grn<1> 2 FB16_15 54 I/O O + grn<2> 2 FB16_16 53 I/O O + Signals Used by Logic in Function Block 1: D<1>.PIN 4: D<4>.PIN 7: D<7>.PIN 2: D<2>.PIN 5: D<5>.PIN 8: xclk 3: D<3>.PIN 6: D<6>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs red<1> X......X................................ 2 red<2> .X.....X................................ 2 red<3> ..X....X................................ 2 red<4> ...X...X................................ 2 grn<0> ....X..X................................ 2 grn<1> .....X.X................................ 2 grn<2> ......XX................................ 2 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** A(0) <= NOT (((NOT wra(0) AND xclk) OR (NOT xclk AND NOT rda(0)))); A(1) <= NOT (((xclk AND NOT wra(1)) OR (NOT xclk AND NOT rda(1)))); A(2) <= NOT (((xclk AND NOT wra(2)) OR (NOT xclk AND NOT rda(2)))); A(3) <= NOT (((xclk AND NOT wra(3)) OR (NOT xclk AND NOT rda(3)))); A(4) <= NOT (((xclk AND NOT wra(4)) OR (NOT xclk AND NOT rda(4)))); A(5) <= NOT (((xclk AND NOT wra(5)) OR (NOT xclk AND NOT rda(5)))); A(6) <= NOT (((xclk AND NOT wra(6)) OR (NOT xclk AND NOT rda(6)))); A(7) <= NOT (((xclk AND NOT wra(7)) OR (NOT xclk AND NOT rda(7)))); A(8) <= NOT (((xclk AND NOT wra(8)) OR (NOT xclk AND NOT rda(8)))); A(9) <= NOT (((xclk AND NOT wra(9)) OR (NOT xclk AND NOT rda(9)))); A(10) <= NOT (((xclk AND NOT wra(10)) OR (NOT xclk AND NOT rda(10)))); A(11) <= NOT (((xclk AND NOT wra(11)) OR (NOT xclk AND NOT rda(11)))); A(12) <= NOT (((xclk AND NOT wra(12)) OR (NOT xclk AND NOT rda(12)))); A(13) <= NOT (((xclk AND NOT wra(13)) OR (NOT xclk AND NOT rda(13)))); A(14) <= NOT (((xclk AND NOT wra(14)) OR (NOT xclk AND NOT rda(14)))); A(15) <= NOT (((xclk AND NOT wra(15)) OR (NOT xclk AND NOT rda(15)))); A(16) <= NOT (((xclk AND NOT wra(16)) OR (NOT xclk AND NOT rda(16)))); A(17) <= NOT (((xclk AND NOT wra(17)) OR (NOT xclk AND NOT rda(17)))); A(18) <= NOT (((xclk AND NOT wra(18)) OR (NOT xclk AND NOT rda(18)))); FDCPE_D0: FDCPE port map (D_I(0),udat(0),xclk,'0','0',D_CE(0)); D(0) <= D_I(0) when D_OE(0) = '1' else 'Z'; D_OE(0) <= xclk; D_CE(0) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D1: FDCPE port map (D_I(1),udat(1),xclk,'0','0',D_CE(1)); D(1) <= D_I(1) when D_OE(1) = '1' else 'Z'; D_OE(1) <= xclk; D_CE(1) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D2: FDCPE port map (D_I(2),udat(2),xclk,'0','0',D_CE(2)); D(2) <= D_I(2) when D_OE(2) = '1' else 'Z'; D_OE(2) <= xclk; D_CE(2) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D3: FDCPE port map (D_I(3),udat(3),xclk,'0','0',D_CE(3)); D(3) <= D_I(3) when D_OE(3) = '1' else 'Z'; D_OE(3) <= xclk; D_CE(3) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D4: FDCPE port map (D_I(4),udat(4),xclk,'0','0',D_CE(4)); D(4) <= D_I(4) when D_OE(4) = '1' else 'Z'; D_OE(4) <= xclk; D_CE(4) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D5: FDCPE port map (D_I(5),udat(5),xclk,'0','0',D_CE(5)); D(5) <= D_I(5) when D_OE(5) = '1' else 'Z'; D_OE(5) <= xclk; D_CE(5) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D6: FDCPE port map (D_I(6),udat(6),xclk,'0','0',D_CE(6)); D(6) <= D_I(6) when D_OE(6) = '1' else 'Z'; D_OE(6) <= xclk; D_CE(6) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D7: FDCPE port map (D_I(7),rxd,xclk,'0','0',D_CE(7)); D(7) <= D_I(7) when D_OE(7) = '1' else 'Z'; D_OE(7) <= xclk; D_CE(7) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND NOT rxhi); FDCPE_D8: FDCPE port map (D_I(8),udat(0),xclk,'0','0',D_CE(8)); D(8) <= D_I(8) when D_OE(8) = '1' else 'Z'; D_OE(8) <= xclk; D_CE(8) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D9: FDCPE port map (D_I(9),udat(1),xclk,'0','0',D_CE(9)); D(9) <= D_I(9) when D_OE(9) = '1' else 'Z'; D_OE(9) <= xclk; D_CE(9) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D10: FDCPE port map (D_I(10),udat(2),xclk,'0','0',D_CE(10)); D(10) <= D_I(10) when D_OE(10) = '1' else 'Z'; D_OE(10) <= xclk; D_CE(10) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D11: FDCPE port map (D_I(11),udat(3),xclk,'0','0',D_CE(11)); D(11) <= D_I(11) when D_OE(11) = '1' else 'Z'; D_OE(11) <= xclk; D_CE(11) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D12: FDCPE port map (D_I(12),udat(4),xclk,'0','0',D_CE(12)); D(12) <= D_I(12) when D_OE(12) = '1' else 'Z'; D_OE(12) <= xclk; D_CE(12) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D13: FDCPE port map (D_I(13),udat(5),xclk,'0','0',D_CE(13)); D(13) <= D_I(13) when D_OE(13) = '1' else 'Z'; D_OE(13) <= xclk; D_CE(13) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D14: FDCPE port map (D_I(14),udat(6),xclk,'0','0',D_CE(14)); D(14) <= D_I(14) when D_OE(14) = '1' else 'Z'; D_OE(14) <= xclk; D_CE(14) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); FDCPE_D15: FDCPE port map (D_I(15),rxd,xclk,'0','0',D_CE(15)); D(15) <= D_I(15) when D_OE(15) = '1' else 'Z'; D_OE(15) <= xclk; D_CE(15) <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi); LED <= NOT ((NOT wra(0) AND NOT wra(10) AND NOT wra(1) AND NOT wra(2) AND NOT wra(3) AND NOT wra(4) AND NOT wra(5) AND NOT wra(6) AND NOT wra(7) AND NOT wra(8) AND NOT wra(9) AND NOT wra(11) AND wra(12) AND wra(13) AND NOT wra(14) AND wra(15) AND NOT wra(16) AND NOT wra(17) AND wra(18))); N_PZ_639 <= ((rcnt(3) AND rcnt(9)) OR (rcnt(9) AND rcnt(4)) OR (rcnt(9) AND rcnt(1)) OR (rcnt(9) AND rcnt(5)) OR (rcnt(9) AND rcnt(2)) OR (rcnt(9) AND rcnt(6)) OR (rcnt(9) AND rcnt(7)) OR (rcnt(9) AND rcnt(8)) OR (pcnt(8) AND pcnt(9)) OR (NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(9) AND NOT pcnt(7)) OR (NOT pcnt(8) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7)) OR (NOT rcnt(9) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (pcnt(2) AND pcnt(5) AND pcnt(6) AND pcnt(9) AND pcnt(7)) OR (pcnt(3) AND pcnt(5) AND pcnt(6) AND pcnt(9) AND pcnt(7)) OR (pcnt(5) AND pcnt(4) AND pcnt(6) AND pcnt(9) AND pcnt(7)) OR (NOT pcnt(2) AND NOT pcnt(3) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(9) AND NOT pcnt(7)) OR (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT rcnt(1) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8))); N_PZ_653 <= ((NOT pcnt(8)) OR (NOT pcnt(9)) OR (NOT pcnt(5) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(7)) OR (NOT pcnt(2) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(6) AND NOT pcnt(7)) OR (NOT pcnt(1) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(6) AND NOT pcnt(7))); N_PZ_677 <= ((ucnt(1) AND NOT ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(2) AND NOT ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND NOT ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); N_PZ_935 <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); N_PZ_936 <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); RD <= NOT ((NOT xclk AND yclk)); WR <= NOT ((rxcf AND xclk AND NOT yclk)); LDCP_blu0: LDCP port map (blu(0),D(11).PIN,NOT xclk,'0','0'); LDCP_blu1: LDCP port map (blu(1),D(12).PIN,NOT xclk,'0','0'); LDCP_blu2: LDCP port map (blu(2),D(13).PIN,NOT xclk,'0','0'); LDCP_blu3: LDCP port map (blu(3),D(14).PIN,NOT xclk,'0','0'); LDCP_blu4: LDCP port map (blu(4),D(15).PIN,NOT xclk,'0','0'); LDCP_grn0: LDCP port map (grn(0),D(5).PIN,NOT xclk,'0','0'); LDCP_grn1: LDCP port map (grn(1),D(6).PIN,NOT xclk,'0','0'); LDCP_grn2: LDCP port map (grn(2),D(7).PIN,NOT xclk,'0','0'); LDCP_grn3: LDCP port map (grn(3),D(8).PIN,NOT xclk,'0','0'); LDCP_grn4: LDCP port map (grn(4),D(9).PIN,NOT xclk,'0','0'); LDCP_grn5: LDCP port map (grn(5),D(10).PIN,NOT xclk,'0','0'); hsync <= ((NOT pcnt(8)) OR (NOT pcnt(9)) OR (NOT pcnt(2) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(7)) OR (NOT pcnt(1) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(7))); pclk <= (xclk AND yclk); FDCPE_pcnt0: FDCPE port map (pcnt(0),pcnt_D(0),xclk,'0','0','1'); pcnt_D(0) <= (N_PZ_653 AND NOT pcnt(0)); FDCPE_pcnt1: FDCPE port map (pcnt(1),pcnt_D(1),xclk,'0','0','1'); pcnt_D(1) <= ((N_PZ_653 AND pcnt(1) AND NOT pcnt(0)) OR (N_PZ_653 AND NOT pcnt(1) AND pcnt(0))); FTCPE_pcnt2: FTCPE port map (pcnt(2),pcnt_T(2),xclk,'0','0','1'); pcnt_T(2) <= ((NOT N_PZ_653 AND pcnt(2)) OR (N_PZ_653 AND pcnt(1) AND pcnt(0))); FDCPE_pcnt3: FDCPE port map (pcnt(3),pcnt_D(3),xclk,'0','0','1'); pcnt_D(3) <= (N_PZ_653 AND pcnt(3)) XOR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0)); FDCPE_pcnt4: FDCPE port map (pcnt(4),pcnt_D(4),xclk,'0','0','1'); pcnt_D(4) <= (N_PZ_653 AND pcnt(4)) XOR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3)); FTCPE_pcnt5: FTCPE port map (pcnt(5),pcnt_T(5),xclk,'0','0','1'); pcnt_T(5) <= ((pcnt(5) AND pcnt(8) AND pcnt(9)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND NOT pcnt(8) AND pcnt(4)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(4) AND NOT pcnt(9))); FTCPE_pcnt6: FTCPE port map (pcnt(6),pcnt_T(6),xclk,'0','0','1'); pcnt_T(6) <= ((pcnt(8) AND pcnt(6) AND pcnt(9)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND NOT pcnt(8) AND pcnt(4)) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(4) AND NOT pcnt(9))); FTCPE_pcnt7: FTCPE port map (pcnt(7),pcnt_T(7),xclk,'0','0','1'); pcnt_T(7) <= ((NOT N_PZ_653 AND pcnt(7)) OR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(4) AND pcnt(6))); FTCPE_pcnt8: FTCPE port map (pcnt(8),pcnt_T(8),xclk,'0','0','1'); pcnt_T(8) <= ((NOT N_PZ_653) OR (pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(4) AND pcnt(6) AND pcnt(7))); FDCPE_pcnt9: FDCPE port map (pcnt(9),pcnt_D(9),xclk,'0','0','1'); pcnt_D(9) <= ((N_PZ_653 AND pcnt(9)) OR (N_PZ_653 AND pcnt(2) AND pcnt(1) AND pcnt(0) AND pcnt(3) AND pcnt(5) AND pcnt(8) AND pcnt(4) AND pcnt(6) AND pcnt(7))); FDCPE_rcnt0: FDCPE port map (rcnt(0),rcnt_D(0),xclk,'0','0','1'); rcnt_D(0) <= ((N_PZ_653 AND rcnt(0)) OR (NOT rcnt(9) AND NOT N_PZ_653 AND NOT rcnt(0)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); FTCPE_rcnt1: FTCPE port map (rcnt(1),rcnt_T(1),xclk,'0','0','1'); rcnt_T(1) <= (rcnt(9) AND NOT N_PZ_653 AND rcnt(1)) XOR ((NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(0)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(6) AND rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); FTCPE_rcnt2: FTCPE port map (rcnt(2),rcnt_T(2),xclk,'0','0','1'); rcnt_T(2) <= (rcnt(9) AND NOT N_PZ_653 AND rcnt(2)) XOR ((NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(0)) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(1) AND NOT rcnt(5) AND rcnt(2) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT N_PZ_653 AND NOT rcnt(5) AND rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); FTCPE_rcnt3: FTCPE port map (rcnt(3),rcnt_T(3),xclk,'0','0','1'); rcnt_T(3) <= ((rcnt(3) AND rcnt(9) AND NOT N_PZ_653) OR (NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(2) AND rcnt(0)) OR (NOT rcnt(3) AND NOT rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND NOT rcnt(5) AND rcnt(2) AND NOT rcnt(6) AND rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8))); FTCPE_rcnt4: FTCPE port map (rcnt(4),rcnt_T(4),xclk,'0','0','1'); rcnt_T(4) <= ((rcnt(9) AND rcnt(4) AND NOT N_PZ_653) OR (rcnt(3) AND NOT rcnt(9) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(2) AND rcnt(0))); FTCPE_rcnt5: FTCPE port map (rcnt(5),rcnt_T(5),xclk,'0','0','1'); rcnt_T(5) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(5)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(2) AND rcnt(0))); FTCPE_rcnt6: FTCPE port map (rcnt(6),rcnt_T(6),xclk,'0','0','1'); rcnt_T(6) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(6)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(0))); FTCPE_rcnt7: FTCPE port map (rcnt(7),rcnt_T(7),xclk,'0','0','1'); rcnt_T(7) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(7)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(6) AND rcnt(0))); FTCPE_rcnt8: FTCPE port map (rcnt(8),rcnt_T(8),xclk,'0','0','1'); rcnt_T(8) <= ((rcnt(9) AND NOT N_PZ_653 AND rcnt(8)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(6) AND rcnt(0) AND rcnt(7))); FDCPE_rcnt9: FDCPE port map (rcnt(9),rcnt_D(9),xclk,'0','0','1'); rcnt_D(9) <= ((rcnt(9) AND N_PZ_653) OR (NOT rcnt(3) AND rcnt(9) AND NOT rcnt(4) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (rcnt(3) AND NOT rcnt(9) AND rcnt(4) AND NOT N_PZ_653 AND rcnt(1) AND rcnt(5) AND rcnt(2) AND rcnt(6) AND rcnt(0) AND rcnt(7) AND rcnt(8))); FTCPE_rda0: FTCPE port map (rda(0),NOT N_PZ_639,xclk,rda_CLR(0),'0','1'); rda_CLR(0) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda1: FTCPE port map (rda(1),rda_T(1),xclk,rda_CLR(1),'0','1'); rda_T(1) <= (rda(0) AND NOT N_PZ_639); rda_CLR(1) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda2: FTCPE port map (rda(2),rda_T(2),xclk,rda_CLR(2),'0','1'); rda_T(2) <= (rda(0) AND NOT N_PZ_639 AND rda(1)); rda_CLR(2) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda3: FTCPE port map (rda(3),rda_T(3),xclk,rda_CLR(3),'0','1'); rda_T(3) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2)); rda_CLR(3) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda4: FTCPE port map (rda(4),rda_T(4),xclk,rda_CLR(4),'0','1'); rda_T(4) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3)); rda_CLR(4) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda5: FTCPE port map (rda(5),rda_T(5),xclk,rda_CLR(5),'0','1'); rda_T(5) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4)); rda_CLR(5) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda6: FTCPE port map (rda(6),rda_T(6),xclk,rda_CLR(6),'0','1'); rda_T(6) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5)); rda_CLR(6) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda7: FTCPE port map (rda(7),rda_T(7),xclk,rda_CLR(7),'0','1'); rda_T(7) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6)); rda_CLR(7) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda8: FTCPE port map (rda(8),rda_T(8),xclk,rda_CLR(8),'0','1'); rda_T(8) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7)); rda_CLR(8) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda9: FTCPE port map (rda(9),rda_T(9),xclk,rda_CLR(9),'0','1'); rda_T(9) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8)); rda_CLR(9) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda10: FTCPE port map (rda(10),rda_T(10),xclk,rda_CLR(10),'0','1'); rda_T(10) <= (rda(0) AND NOT N_PZ_639 AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9)); rda_CLR(10) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda11: FTCPE port map (rda(11),rda_T(11),xclk,rda_CLR(11),'0','1'); rda_T(11) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9)); rda_CLR(11) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda12: FTCPE port map (rda(12),rda_T(12),xclk,rda_CLR(12),'0','1'); rda_T(12) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11)); rda_CLR(12) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda13: FTCPE port map (rda(13),rda_T(13),xclk,rda_CLR(13),'0','1'); rda_T(13) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12)); rda_CLR(13) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda14: FTCPE port map (rda(14),rda_T(14),xclk,rda_CLR(14),'0','1'); rda_T(14) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13)); rda_CLR(14) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda15: FTCPE port map (rda(15),rda_T(15),xclk,rda_CLR(15),'0','1'); rda_T(15) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14)); rda_CLR(15) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda16: FTCPE port map (rda(16),rda_T(16),xclk,rda_CLR(16),'0','1'); rda_T(16) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14) AND rda(15)); rda_CLR(16) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_rda17: FTCPE port map (rda(17),rda_T(17),xclk,N_PZ_936,'0','1'); rda_T(17) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14) AND rda(15) AND rda(16)); FTCPE_rda18: FTCPE port map (rda(18),rda_T(18),xclk,N_PZ_935,'0','1'); rda_T(18) <= (rda(0) AND NOT N_PZ_639 AND rda(10) AND rda(1) AND rda(2) AND rda(3) AND rda(4) AND rda(5) AND rda(6) AND rda(7) AND rda(8) AND rda(9) AND rda(11) AND rda(12) AND rda(13) AND rda(14) AND rda(15) AND rda(16) AND rda(17)); LDCP_red0: LDCP port map (red(0),D(0).PIN,NOT xclk,'0','0'); LDCP_red1: LDCP port map (red(1),D(1).PIN,NOT xclk,'0','0'); LDCP_red2: LDCP port map (red(2),D(2).PIN,NOT xclk,'0','0'); LDCP_red3: LDCP port map (red(3),D(3).PIN,NOT xclk,'0','0'); LDCP_red4: LDCP port map (red(4),D(4).PIN,NOT xclk,'0','0'); FDCPE_rxcf: FDCPE port map (rxcf,rxcf_D,xclk,'0','0','1'); rxcf_D <= ((rxcf AND udiv(0) AND udiv(1) AND udiv(2)) OR (rxcf AND NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0)) OR (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2) AND rxhi)); FTCPE_rxhi: FTCPE port map (rxhi,rxhi_T,xclk,'0','0','1'); rxhi_T <= (NOT ucnt(1) AND NOT ucnt(2) AND ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2)); FTCPE_ucnt0: FTCPE port map (ucnt(0),ucnt_T(0),xclk,'0','0','1'); ucnt_T(0) <= ((NOT ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0)) OR (NOT ucnt(1) AND NOT ucnt(2) AND udiv(0) AND udiv(1) AND udiv(2))); FTCPE_ucnt1: FTCPE port map (ucnt(1),ucnt_T(1),xclk,'0','0','1'); ucnt_T(1) <= ((ucnt(1) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT ucnt(2) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2)) OR (NOT ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); FTCPE_ucnt2: FTCPE port map (ucnt(2),ucnt_T(2),xclk,'0','0','1'); ucnt_T(2) <= ((ucnt(2) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(1) AND NOT ucnt(3) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); FTCPE_ucnt3: FTCPE port map (ucnt(3),ucnt_T(3),xclk,'0','0','1'); ucnt_T(3) <= ((ucnt(1) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(2) AND ucnt(3) AND udiv(0) AND udiv(1) AND udiv(2)) OR (ucnt(1) AND ucnt(2) AND ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); FDCPE_udat0: FDCPE port map (udat(0),udat(1),xclk,'0','0',N_PZ_677); FDCPE_udat1: FDCPE port map (udat(1),udat(2),xclk,'0','0',N_PZ_677); FDCPE_udat2: FDCPE port map (udat(2),udat(3),xclk,'0','0',N_PZ_677); FDCPE_udat3: FDCPE port map (udat(3),udat(4),xclk,'0','0',N_PZ_677); FDCPE_udat4: FDCPE port map (udat(4),udat(5),xclk,'0','0',N_PZ_677); FDCPE_udat5: FDCPE port map (udat(5),udat(6),xclk,'0','0',N_PZ_677); FDCPE_udat6: FDCPE port map (udat(6),rxd,xclk,'0','0',N_PZ_677); FTCPE_udiv0: FTCPE port map (udiv(0),udiv_T(0),xclk,'0','0','1'); udiv_T(0) <= NOT (((NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(0)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(1)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(2)))); FTCPE_udiv1: FTCPE port map (udiv(1),udiv_T(1),xclk,'0','0','1'); udiv_T(1) <= udiv(0) XOR ((NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND NOT udiv(1)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND NOT udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(0) AND udiv(1))); FTCPE_udiv2: FTCPE port map (udiv(2),udiv_T(2),xclk,'0','0','1'); udiv_T(2) <= (udiv(0) AND udiv(1)) XOR ((NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(0) AND NOT udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND NOT udiv(1) AND NOT udiv(2)) OR (rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND udiv(1) AND NOT udiv(2)) OR (NOT rxd AND NOT ucnt(1) AND NOT ucnt(2) AND NOT ucnt(3) AND NOT ucnt(0) AND udiv(0) AND udiv(1) AND udiv(2))); vsync <= NOT (((NOT rcnt(9) AND NOT rcnt(4) AND NOT rcnt(5) AND NOT rcnt(6) AND NOT rcnt(7) AND NOT rcnt(8)) OR (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)))); FTCPE_wra0: FTCPE port map (wra(0),'0',rxcf,wra_CLR(0),'0','1'); wra_CLR(0) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra1: FTCPE port map (wra(1),wra(0),rxcf,wra_CLR(1),'0','1'); wra_CLR(1) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra2: FTCPE port map (wra(2),wra_T(2),rxcf,wra_CLR(2),'0','1'); wra_T(2) <= (wra(0) AND wra(1)); wra_CLR(2) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra3: FTCPE port map (wra(3),wra_T(3),rxcf,wra_CLR(3),'0','1'); wra_T(3) <= (wra(0) AND wra(1) AND wra(2)); wra_CLR(3) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra4: FTCPE port map (wra(4),wra_T(4),rxcf,wra_CLR(4),'0','1'); wra_T(4) <= (wra(0) AND wra(1) AND wra(2) AND wra(3)); wra_CLR(4) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra5: FTCPE port map (wra(5),wra_T(5),rxcf,wra_CLR(5),'0','1'); wra_T(5) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4)); wra_CLR(5) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra6: FTCPE port map (wra(6),wra_T(6),rxcf,wra_CLR(6),'0','1'); wra_T(6) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5)); wra_CLR(6) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra7: FTCPE port map (wra(7),wra_T(7),rxcf,wra_CLR(7),'0','1'); wra_T(7) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6)); wra_CLR(7) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra8: FTCPE port map (wra(8),wra_T(8),rxcf,wra_CLR(8),'0','1'); wra_T(8) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7)); wra_CLR(8) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra9: FTCPE port map (wra(9),wra_T(9),rxcf,wra_CLR(9),'0','1'); wra_T(9) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8)); wra_CLR(9) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra10: FTCPE port map (wra(10),wra_T(10),rxcf,wra_CLR(10),'0','1'); wra_T(10) <= (wra(0) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9)); wra_CLR(10) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra11: FTCPE port map (wra(11),wra_T(11),rxcf,wra_CLR(11),'0','1'); wra_T(11) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9)); wra_CLR(11) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra12: FTCPE port map (wra(12),wra_T(12),rxcf,wra_CLR(12),'0','1'); wra_T(12) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11)); wra_CLR(12) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra13: FTCPE port map (wra(13),wra_T(13),rxcf,wra_CLR(13),'0','1'); wra_T(13) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12)); wra_CLR(13) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra14: FTCPE port map (wra(14),wra_T(14),rxcf,wra_CLR(14),'0','1'); wra_T(14) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13)); wra_CLR(14) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra15: FTCPE port map (wra(15),wra_T(15),rxcf,wra_CLR(15),'0','1'); wra_T(15) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14)); wra_CLR(15) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra16: FTCPE port map (wra(16),wra_T(16),rxcf,wra_CLR(16),'0','1'); wra_T(16) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14) AND wra(15)); wra_CLR(16) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra17: FTCPE port map (wra(17),wra_T(17),rxcf,wra_CLR(17),'0','1'); wra_T(17) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14) AND wra(15) AND wra(16)); wra_CLR(17) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wra18: FTCPE port map (wra(18),wra_T(18),rxcf,wra_CLR(18),'0','1'); wra_T(18) <= (wra(0) AND wra(10) AND wra(1) AND wra(2) AND wra(3) AND wra(4) AND wra(5) AND wra(6) AND wra(7) AND wra(8) AND wra(9) AND wra(11) AND wra(12) AND wra(13) AND wra(14) AND wra(15) AND wra(16) AND wra(17)); wra_CLR(18) <= (wrst(0) AND wrst(1) AND wrst(2) AND wrst(3) AND wrst(4)); FTCPE_wrst0: FTCPE port map (wrst(0),wrst_T(0),xclk,rxcf,'0','1'); wrst_T(0) <= (NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_wrst1: FTCPE port map (wrst(1),wrst_T(1),xclk,rxcf,'0','1'); wrst_T(1) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8)); FTCPE_wrst2: FTCPE port map (wrst(2),wrst_T(2),xclk,rxcf,'0','1'); wrst_T(2) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8) AND wrst(1)); FTCPE_wrst3: FTCPE port map (wrst(3),wrst_T(3),xclk,rxcf,'0','1'); wrst_T(3) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8) AND wrst(1) AND wrst(2)); FTCPE_wrst4: FTCPE port map (wrst(4),wrst_T(4),xclk,rxcf,'0','1'); wrst_T(4) <= (wrst(0) AND NOT rcnt(3) AND NOT rcnt(9) AND NOT rcnt(4) AND NOT pcnt(2) AND NOT pcnt(1) AND NOT pcnt(0) AND NOT pcnt(3) AND NOT pcnt(5) AND NOT pcnt(8) AND NOT pcnt(4) AND NOT pcnt(6) AND NOT pcnt(9) AND NOT pcnt(7) AND NOT rcnt(1) AND NOT rcnt(5) AND NOT rcnt(2) AND NOT rcnt(6) AND NOT rcnt(0) AND NOT rcnt(7) AND NOT rcnt(8) AND wrst(1) AND wrst(2) AND wrst(3)); FDDCPE_xclk: FDDCPE port map (xclk,yclk,iclk,'0','0','1'); FDDCPE_yclk: FDDCPE port map (yclk,NOT xclk,iclk,'0','0','1'); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C256-7-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCCIO-3.3 2 KPR 74 KPR 3 KPR 75 KPR 4 KPR 76 KPR 5 KPR 77 KPR 6 KPR 78 KPR 7 KPR 79 KPR 8 VCCAUX 80 KPR 9 KPR 81 KPR 10 KPR 82 KPR 11 KPR 83 KPR 12 KPR 84 VCC 13 KPR 85 KPR 14 KPR 86 KPR 15 KPR 87 rxd 16 KPR 88 KPR 17 KPR 89 GND 18 KPR 90 GND 19 KPR 91 KPR 20 KPR 92 LED 21 KPR 93 VCCIO-3.3 22 KPR 94 KPR 23 KPR 95 KPR 24 KPR 96 KPR 25 KPR 97 KPR 26 KPR 98 KPR 27 VCCIO-3.3 99 GND 28 KPR 100 KPR 29 GND 101 D<12> 30 KPR 102 D<13> 31 KPR 103 D<6> 32 KPR 104 D<7> 33 KPR 105 RD 34 KPR 106 A<8> 35 KPR 107 A<7> 36 GND 108 GND 37 VCC 109 VCCIO-3.3 38 iclk 110 A<6> 39 KPR 111 A<5> 40 KPR 112 A<4> 41 KPR 113 A<3> 42 KPR 114 A<2> 43 KPR 115 A<1> 44 blu<4> 116 A<0> 45 blu<3> 117 D<0> 46 blu<2> 118 D<1> 47 GND 119 D<11> 48 blu<1> 120 D<10> 49 blu<0> 121 D<8> 50 grn<5> 122 TDO 51 grn<4> 123 GND 52 grn<3> 124 D<9> 53 grn<2> 125 D<2> 54 grn<1> 126 D<3> 55 VCCIO-3.3 127 VCCIO-3.3 56 grn<0> 128 WR 57 red<4> 129 A<17> 58 red<3> 130 A<16> 59 red<2> 131 A<15> 60 red<1> 132 A<14> 61 red<0> 133 A<13> 62 GND 134 A<18> 63 TDI 135 A<12> 64 vsync 136 A<11> 65 TMS 137 A<10> 66 hsync 138 A<9> 67 TCK 139 D<4> 68 pclk 140 D<5> 69 KPR 141 VCCIO-3.3 70 KPR 142 D<15> 71 KPR 143 D<14> 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c256-7-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : OFF Global Set/Reset Optimization : OFF Global Ouput Enable Optimization : OFF Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS33 Input Limit : 32 Pterm Limit : 28